High-speed Triple Differential OR/NOR Line Receiver integrated circuit designed under the ECL (Emitter-Coupled Logic) standard. Technical Specifications • Logic Family: ECL (10K Series / High-Speed). • Function: Triple Differential Amplifier / Line Receiver, optimized for tracking, amplifying, and stabilizing weak differential data signals transmitted across long interface cables. • Core Application: Commonly engineered as a high-speed logic interface buffer, data line receiver, or a stable Schmitt Trigger using its built-in Reference Bias Voltage (\(V_{BB}\)) pin out. • Performance Attributes: Typically features an ultra-low propagation delay of roughly 1.5ns and a standard operating current demand of 20mA. • Package Profile: Standard 16-pin vintage ceramic or plastic dual in-line package (DIP).